[pypy-svn] r52806 - in pypy/branch/gameboy-emulator/pypy/lang/gameboy: . test
cami at codespeak.net
cami at codespeak.net
Fri Mar 21 16:18:44 CET 2008
Author: cami
Date: Fri Mar 21 16:18:44 2008
New Revision: 52806
Modified:
pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py
pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py
Log:
jr_cc_nn tests working
Modified: pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py
==============================================================================
--- pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py (original)
+++ pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py Fri Mar 21 16:18:44 2008
@@ -255,6 +255,9 @@
data = self.memory.read(self.pc.get())
self.pc.inc() # 2 cycles
return data
+
+ def fetchDoubleRegister(self, register):
+ self.popDoubleRegister(CPU.fetch, register)
# Stack, 2 cycles
def push(self, data):
@@ -274,12 +277,13 @@
return data
# 3 cycles
- def popDoubleRegister(self, register, getter):
- b = getter() # 1 cycle
- a = getter() # 1 cycle
+ def popDoubleRegister(self, getter, register):
+ b = getter(self) # 1 cycle
+ a = getter(self) # 1 cycle
register.set(a, b) # 2 cycles
self.cycles += 1
+
# 4 cycles
def call(self, address):
self.push(self.pc.getHi()) # 2 cycles
@@ -290,6 +294,10 @@
# 1 cycle
def ld(self, getter, setter):
setter(getter()) # 1 cycle
+
+ def fetchLoad(self, register):
+ self.ld(self.fetch, register.set)
+
# ALU, 1 cycle
def addA(self, data):
@@ -303,14 +311,15 @@
# 2 cycles
def addHL(self, register):
- s = (self.hl.get() + register.get()) & 0xFFFF
+ self.hl.set(self.hl.get() + register.get()); # 1 cycle
+ s = self.hl.get()
self.f.set((self.f.get() & constants.Z_FLAG), False)
if ((s >> 8) & 0x0F) < (self.hl.getHi() & 0x0F):
self.f.add(constants.H_FLAG, False)
if s < self.hl.get():
self.f.add(constants.C_FLAG, False)
self.cycles -= 1
- self.hl.set(s); # 1 cycle
+
# 1 cycle
def adc(self, getter):
@@ -685,10 +694,10 @@
self.pc.add(2) # 3 cycles
def isNZ(self):
- return (self.f.get() & constants.Z_FLAG) == 0
+ return not self.isZ()
def isNC(self):
- return (self.f.get() & constants.C_FLAG) == 0
+ return not self.isC()
def isZ(self):
return (self.f.get() & constants.Z_FLAG) != 0
@@ -783,14 +792,12 @@
def group_lambda(function, register, value=None):
if value == None:
- lambda s: function(s, register.get, register.set)
+ return lambda s: function(s, register.get, register.set)
else:
- lambda s: function(s, register.get, register.set, value)
+ return lambda s: function(s, register.get, register.set, value)
-
def create_register_op_codes(table):
- print ""
opCodes = []
for entry in table:
opCode = entry[0]
@@ -805,10 +812,11 @@
return opCodes
def register_lambda(function, registerOrGetter):
- if registerOrGetter is object:
- return lambda s: function(s, registerOrGetter)
- else:
+ if callable(registerOrGetter):
return lambda s: function(s, registerOrGetter(s))
+ else:
+ return lambda s: function(s, registerOrGetter)
+
def initialize_op_code_table(table):
print ""
@@ -821,15 +829,7 @@
else:
positions = range(entry[0], entry[1]+1)
for pos in positions:
- #try:
- # print "D1", hex(pos), entry[-1].func_closure[0].cell_contents.func_name
- #except:
- # pass
- #else:
- # print "D2", hex(pos), entry[-1]
- #print ""
result[pos] = entry[-1]
- #assert result[pos] is None
return result
# OPCODE TABLES ---------------------------------------------------------------
@@ -902,15 +902,13 @@
(0xA8, 0x01, CPU.XOR),
(0xB0, 0x01, CPU.OR),
(0xB8, 0x01, CPU.cpA),
- (0x06, 0x08, lambda s, register:CPU.ld(s, CPU.fetch(s), register.set)),
+ (0x06, 0x08, CPU.fetchLoad),
(0x40, 0x01, CPU.res, range(0, 8))
]
REGISTER_OP_CODES = [
- (0x01, 0x10, lambda s, register: CPU.popDoubleRegister(s, register=register,\
- getter=CPU.fetch),\
- [CPU.bc, CPU.de, CPU.hl, CPU.sp]),
+ (0x01, 0x10, CPU.fetchDoubleRegister, [CPU.bc, CPU.de, CPU.hl, CPU.sp]),
(0x09, 0x10, CPU.addHL, [CPU.bc, CPU.de, CPU.hl, CPU.sp]),
(0x03, 0x10, CPU.incDoubleRegister, [CPU.bc, CPU.de, CPU.hl, CPU.sp]),
(0x0B, 0x10, CPU.decDoubleRegister, [CPU.bc, CPU.de, CPU.hl, CPU.sp]),
@@ -939,9 +937,9 @@
# RAW OPCODE TABLE INITIALIZATION ----------------------------------------------
FIRST_ORDER_OP_CODES += create_register_op_codes(REGISTER_OP_CODES)
-#FIRST_ORDER_OP_CODES += create_group_op_codes(REGISTER_GROUP_OP_CODES)
+FIRST_ORDER_OP_CODES += create_group_op_codes(REGISTER_GROUP_OP_CODES)
SECOND_ORDER_OP_CODES = create_group_op_codes(SECOND_ORDER_REGISTER_GROUP_OP_CODES)
OP_CODES = initialize_op_code_table(FIRST_ORDER_OP_CODES)
-FETCH_EXECUTE_OP_CODES = []#initialize_op_code_table(SECOND_ORDER_OP_CODES)
+FETCH_EXECUTE_OP_CODES = initialize_op_code_table(SECOND_ORDER_OP_CODES)
Modified: pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py
==============================================================================
--- pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py (original)
+++ pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py Fri Mar 21 16:18:44 2008
@@ -174,6 +174,33 @@
assert cpu.pc.get() == pc+1
+def test_flags():
+ cpu = get_cpu()
+ cpu.f.set(constants.Z_FLAG)
+ assert cpu.isZ() == True
+ assert cpu.isNZ() == False
+ cpu.f.set(~constants.Z_FLAG)
+ assert cpu.isZ() == False
+ assert cpu.isNZ() == True
+
+ cpu.f.set(constants.C_FLAG)
+ assert cpu.isC() == True
+ assert cpu.isNC() == False
+ cpu.f.set(~constants.C_FLAG)
+ assert cpu.isC() == False
+ assert cpu.isNC() == True
+
+def test_flags_memory_access():
+ cpu = get_cpu()
+ cpu.f.set(constants.Z_FLAG)
+ assert cpu.isZ() == True
+ prepare_for_fetch(cpu, 0x1234, 0x1234)
+ cpu.memory.write(0x1234, 0x12)
+ assert cpu.isZ() == True
+ cpu.rom[0x1234] = 0x12
+ assert cpu.isZ() == True
+
+
def cycle_test(cpu, opCode, cycles=0):
startCycles = cpu.cycles
try:
@@ -191,7 +218,6 @@
# TEST HELPERS ---------------------------------------
def test_create_group_op_codes():
- py.test.skip()
assert len(GROUPED_REGISTERS) == 8
start=0x12
step=0x03
@@ -210,7 +236,6 @@
def test_create_register_op_codes():
- py.test.skip()
start = 0x09
step = 0x10
func = CPU.addHL
@@ -231,7 +256,6 @@
de=constants.RESET_DE, f=constants.RESET_F,\
hl=constants.RESET_HL, sp=constants.RESET_SP,\
pc=constants.RESET_PC):
-
return assert_registers(cpu, a, bc, de, f, hl, sp, pc)
def assert_registers(cpu, a=None, bc=None, de=None, f=None, hl=None, sp=None, pc=None):
@@ -251,9 +275,11 @@
assert cpu.pc.get() == pc, "Register pc is %s but should be %s" % (hex(cpu.pc.get()), hex(pc))
def prepare_for_fetch(cpu, value, valueLo=None):
- cpu.rom[cpu.pc.get()] = value & 0xFF
+ cpu.rom[cpu.pc.get()] = value
+ cpu.memory.write(cpu.pc.get(), value & 0xFF)
if valueLo is not None:
- cpu.rom[cpu.pc.get()+1] = value & 0xFF
+ cpu.rom[cpu.pc.get()+1] = valueLo & 0xFF
+ cpu.memory.write(cpu.pc.get(), valueLo & 0xFF)
def set_registers(registers, value):
#if registers is not list:
@@ -303,7 +329,6 @@
# jr_NZ_nn see test_jr_cc_nn
def test_0x20_0x28_0x30():
- #py.test.skip("OpCode Table incomplete")
cpu = get_cpu()
flags = [~constants.Z_FLAG, constants.Z_FLAG, ~constants.C_FLAG, constants.C_FLAG]
opCode = 0x20
@@ -319,7 +344,8 @@
cpu.f.set(~flags[i])
cycle_test(cpu, opCode, 2)
assert cpu.pc.get() == pc+1
- value += 2
+ value += 3
+ opCode += 0x08
# ld_BC_nnnn to ld_SP_nnnn
def test_0x01_0x11_0x21_0x31():
@@ -327,12 +353,14 @@
cpu = get_cpu()
registers= [cpu.bc, cpu.de, cpu.hl, cpu.sp]
value = 0x12
+ opCode = 0x01
for index in range(0, 8):
prepare_for_fetch(cpu, value, value+1)
- cycle_test(cpu, 0x01+index*0x10, 3)
+ cycle_test(cpu, opCode, 3)
assert registers[index].getHi() == value
assert registers[index].getlo() == value+1
- value += 2
+ value += 3
+ opCode += 0x10
# add_HL_BC to add_HL_SP
def test_0x09_0x19_0x29_0x39():
@@ -340,13 +368,15 @@
cpu = get_cpu()
registers= [cpu.bc, cpu.de, cpu.hl, cpu.sp]
value = 0x1234
+ opCode = 0x09
for i in range(0, 8):
- cpu.hl.set(0x00)
+ cpu.hl.set(value)
registers[i].set(value)
assert registers[i].get() == value
- cycle_test(cpu, 0x09+i*0x10, 2)
- assert cpu.hl.get() == value
- value += 1
+ cycle_test(cpu, opCode, 2)
+ assert cpu.hl.get() == value+value
+ value += 3
+ opCode += 0x10
# ld_BCi_A
def test_0x02():
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